`timescale 1ns / 1ns

module d_trigger (
    input clk,
    input clrn,
    input d,
    output reg q
);
    always @(posedge clk or posedge clrn) begin
        if (clrn != 0) begin
            q <= 0;
        end else begin
            q <= d;
        end
    end
endmodule

module RTL (
    input clk,
    input rst_n,
    input data_in,
    output data_out
);
    wire q1;
    d_trigger d1 (
        .clk(clk),
        .clrn(~rst_n),
        .d(data_in),
        .q(q1)
    );
    d_trigger d2 (
        .clk(clk),
        .clrn(~rst_n),
        .d(data_in & ~q1),
        .q(data_out)
    );
endmodule
